First implemented in the Intel Pentium Pro in 1995, it was extended by AMD to add a level to the page table hierarchy, to allow it to handle up to 52-bit physical addresses, add NX bit functionality, and make it the mandatory memory paging model in long mode. PAE is provided by Intel Pentium Pro (and above) CPUs - including all later Pentium-series processors (except the 400 MHz bus versions of the Pentium M), as well as by other processors such as the AMD Athlon and later AMD processor models with similar or more advanced versions of the same architecture.

x86 processor hardware-architecture is augmented with additional address lines used to select the additional memory, so physical address size increases from 32 bits to 36 bits. This, theoretically, increases maximum physical memory size from 4 GB to 64 GB. The 32-bit size of the virtual address is not changed, so regular application software continues to use instructions with 32-bit addresses and (in a flat memory model) is limited to 4 gigabytes of virtual address space. The operating system uses page tables to map this 4-GB address space into the 64 GB of physical memory. The mapping is typically applied differently for each process. In this way, the extra memory is useful even though no single regular application can access it all simultaneously.

To use PAE, operating system support is required. Intel versions of Mac OS X support PAE. The Linux kernel supports PAE as a build option and most major distributions provide a PAE kernel either as the default or as an option. FreeBSD and NetBSD also support PAE as a kernel build option.

Microsoft Windows implements PAE if booted with the appropriate option, but current 32-bit desktop editions enforce the physical address space within 4GB even in PAE mode. According to Geoff Chappell, Microsoft limits 32-bit versions of Windows to 4GB due to a licensing restriction, and Microsoft Technical Fellow Mark Russinovich says that some drivers were found to be unstable when encountering physical addresses above 4GB.. Unofficial kernel patches for Windows Vista 32-bit are available[dubious – discuss] that break this enforced limitation, though the stability is not guaranteed.

For application software which needs access to more than 4 GB of RAM, operating systems may provide some special mechanisms in addition to the regular PAE support. On Windows this mechanism is called Address Windowing Extensions, while on Unix-like systems a variety of techniques are used, such as using mmap() to map regions of a file into and out of the address space as needed.

In traditional 32-bit protected mode, x86 processors use a two-level page translation scheme, where the control register CR3 points to a single 4 kiB long page directory divided 1024 × 4 byte entries that point to 4 kiB long page tables, similarly consisting of 1024 × 4 byte entries pointing to 4 KiB long pages.

Enabling PAE (by setting bit 5, PAE, of the system register CR4) causes major changes to this scheme. By default, the size of each page remains as 4 kiB. Each entry in the page table and page directory grows to 64 bits (8 bytes) rather than 32 bits - to allow for additional address bits; however, the size of tables does not change, so both table and directory now have only 512 entries. Because this allows only one quarter of the entries of the original scheme, an extra level of hierarchy has been added, so CR3 now points to the Page Directory Pointer Table, a short table which contains pointers to 4 page directories.

The entries in the page directory have an additional flag in bit 7, named PS (for page size). If the system has set this bit to 1, the page directory entry does not point to a page table, but to a single large 2 MiB page. The NX bit is another flag in the page directory, in bit 63, to mark pages as no execute. Because the 12 least significant bits of the page table entry's 64 bits are either similar flags or are available for OS-specific data, a maximum of 52 bits can be potentially used in the future to address 252 bytes, or 4 petabytes, of physical memory.

Software can identify via the CPUID flag PAE whether a CPU supports PAE mode.

On x86-64 processors in native long mode, the address translation scheme resembles PAE but with a fourth table, the page-map level 4 table; this and the Page Directory Pointer Table are 512 entries long. 36 bits of virtual page number are translated, giving a virtual address space of up to 256 TB. In the page table entries, in the original specification, 40 bits of physical page number are implemented out of 52 bits possible. Later x86-64 CPUs may implement more bits of physical page number.